A floating gate transistor typically includes a control gate and a floating gate, such that, when provided an electrical charge through channel-hot-carrier (CHC) electron injection or Fowler-Nordheim tunneling, for example, the charge is retained on the floating gate due to isolation by a surrounding insulating oxide. Floating gate transistors are capable of storing an electrical charge for extended periods of time without requiring additional power input. Floating gate transistors are commonly used in non-volatile memory (NVM) devices, such as flash memory, erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM).
Each non-volatile memory integrated circuit generally includes an array of memory cells and logic for reading the stored information, which may be digital, or multi-level. Many non-volatile memory devices are programmable and/or erasable, and thus also include logic for performing program and erase functions. Flash EEPROMs, for example, are capable of electrically programming and reading individual cells in an array and are also capable of erasing the entire memory cell array simultaneously.
Once programmed, a floating gate NVM cell maintains the data programmed for long periods of time in power-off as well as power-on states. Despite its name, however, the non-volatile memory cell is not perfectly non-volatile in nature. In theory, a floating gate programmed at a particular charge level would remain at that level permanently, since the floating gate is insulated by the surrounding material. In reality, a decay of the charge occurs over time due to various factors, including the gradual escape of electrons from the gate. The decay of charge is not entirely predictable. It can be influenced by environmental factors such as mechanical and thermal stress effects or other variables. Given enough time, the decay will eventually return the floating gate to an electrically balanced state. Even partial charge decay may result in erasure or corruption of the data stored in the NVM cell. Additionally, as the electrons leak from the floating gate, the threshold voltage of the NVM cell gradually decreases, which may eventually allow a current flow sufficient to inadvertently turn a programmed cell on when a read voltage is applied. In addition to the gradual decay of charge on the floating gate, programming is also sometimes hampered by an initial loss of charge shortly after programming. Such charge shifts may be caused by material defects or unintended charge transfer due to circuit geometry.
The term “retention” is used to refer to the integrity of the stored non-volatile memory data as a function of time. Constant monitoring in order to verify retention is not only inefficient, but contradictory to the purpose of NVM, which is designed for data storage absent ongoing power input. Another approach for addressing the problem, simply assuming retention and not monitoring or refreshing the NVM, is sometimes used, but this approach is not desirable in applications where either accuracy or reliability are highly important, particularly automotive, medical, and military markets, for example. One of the problems with traditional voltage references is that in order to maintain a relatively constant voltage over time, the circuit requires a continuous draw of current, which is a disadvantage for low-power systems. The voltage reference can be replaced with a floating gate voltage reference, but the voltage gate reference or sample and hold may drift over time, thus requiring refreshing the voltage or sample and hold value. A problem with refresh schemes that rely solely on timer triggers is that retention may be adversely affected by events other than the passage of time. Operating conditions, such as temperature or radiation exposure, for example, may diminish retention by stimulating electron migration or by causing changes in characteristics of the circuit that permanently affect subsequent retention. A timed approach to ensuring NVM retention by periodically refreshing memory does not react to changing operating conditions.
Due to these and other problems and potential problems with the current state of the art, improved floating gate monitoring circuits and methods would be useful and advantageous.